2014-09-13 23:40:36 +00:00
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/*
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* Copyright 2014 The LibYuv Project Authors. All rights reserved.
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*
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* Use of this source code is governed by a BSD-style license
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* that can be found in the LICENSE file in the root of the source
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* tree. An additional intellectual property rights grant can be found
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* in the file PATENTS. All contributing project authors may
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* be found in the AUTHORS file in the root of the source tree.
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*/
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#include "libyuv/row.h"
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2016-01-11 17:19:48 +00:00
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#include "libyuv/rotate_row.h"
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2014-09-13 23:40:36 +00:00
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#include "libyuv/basic_types.h"
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#ifdef __cplusplus
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namespace libyuv {
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extern "C" {
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#endif
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2016-01-11 17:19:48 +00:00
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// This module is for GCC Neon armv8 64 bit.
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2014-09-13 23:40:36 +00:00
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#if !defined(LIBYUV_DISABLE_NEON) && defined(__aarch64__)
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2016-01-11 17:19:48 +00:00
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2014-09-13 23:40:36 +00:00
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static uvec8 kVTbl4x4Transpose =
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2016-01-11 17:19:48 +00:00
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{ 0, 4, 8, 12, 1, 5, 9, 13, 2, 6, 10, 14, 3, 7, 11, 15 };
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2014-09-13 23:40:36 +00:00
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void TransposeWx8_NEON(const uint8* src, int src_stride,
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2016-01-11 17:19:48 +00:00
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uint8* dst, int dst_stride, int width) {
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2016-05-25 21:49:47 +00:00
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const uint8* src_temp;
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2016-01-11 17:19:48 +00:00
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int64 width64 = (int64) width; // Work around clang 3.4 warning.
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2014-09-13 23:40:36 +00:00
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asm volatile (
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// loops are on blocks of 8. loop will stop when
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// counter gets to or below 0. starting the counter
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// at w-8 allow for this
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2016-01-11 17:19:48 +00:00
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"sub %3, %3, #8 \n"
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2014-09-13 23:40:36 +00:00
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// handle 8x8 blocks. this should be the majority of the plane
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2016-01-11 17:19:48 +00:00
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"1: \n"
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"mov %0, %1 \n"
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2014-09-13 23:40:36 +00:00
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MEMACCESS(0)
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2016-01-11 17:19:48 +00:00
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"ld1 {v0.8b}, [%0], %5 \n"
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2014-09-13 23:40:36 +00:00
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MEMACCESS(0)
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2016-01-11 17:19:48 +00:00
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"ld1 {v1.8b}, [%0], %5 \n"
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2014-09-13 23:40:36 +00:00
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MEMACCESS(0)
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2016-01-11 17:19:48 +00:00
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"ld1 {v2.8b}, [%0], %5 \n"
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2014-09-13 23:40:36 +00:00
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MEMACCESS(0)
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2016-01-11 17:19:48 +00:00
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"ld1 {v3.8b}, [%0], %5 \n"
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2014-09-13 23:40:36 +00:00
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MEMACCESS(0)
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2016-01-11 17:19:48 +00:00
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"ld1 {v4.8b}, [%0], %5 \n"
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2014-09-13 23:40:36 +00:00
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MEMACCESS(0)
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2016-01-11 17:19:48 +00:00
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"ld1 {v5.8b}, [%0], %5 \n"
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2014-09-13 23:40:36 +00:00
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MEMACCESS(0)
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2016-01-11 17:19:48 +00:00
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"ld1 {v6.8b}, [%0], %5 \n"
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2014-09-13 23:40:36 +00:00
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MEMACCESS(0)
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2016-01-11 17:19:48 +00:00
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"ld1 {v7.8b}, [%0] \n"
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2014-09-13 23:40:36 +00:00
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2016-01-11 17:19:48 +00:00
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"trn2 v16.8b, v0.8b, v1.8b \n"
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"trn1 v17.8b, v0.8b, v1.8b \n"
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"trn2 v18.8b, v2.8b, v3.8b \n"
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"trn1 v19.8b, v2.8b, v3.8b \n"
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"trn2 v20.8b, v4.8b, v5.8b \n"
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"trn1 v21.8b, v4.8b, v5.8b \n"
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"trn2 v22.8b, v6.8b, v7.8b \n"
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"trn1 v23.8b, v6.8b, v7.8b \n"
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2014-09-13 23:40:36 +00:00
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2016-01-11 17:19:48 +00:00
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"trn2 v3.4h, v17.4h, v19.4h \n"
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"trn1 v1.4h, v17.4h, v19.4h \n"
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"trn2 v2.4h, v16.4h, v18.4h \n"
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"trn1 v0.4h, v16.4h, v18.4h \n"
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"trn2 v7.4h, v21.4h, v23.4h \n"
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"trn1 v5.4h, v21.4h, v23.4h \n"
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"trn2 v6.4h, v20.4h, v22.4h \n"
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"trn1 v4.4h, v20.4h, v22.4h \n"
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2014-09-13 23:40:36 +00:00
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2016-01-11 17:19:48 +00:00
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"trn2 v21.2s, v1.2s, v5.2s \n"
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"trn1 v17.2s, v1.2s, v5.2s \n"
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"trn2 v20.2s, v0.2s, v4.2s \n"
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"trn1 v16.2s, v0.2s, v4.2s \n"
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"trn2 v23.2s, v3.2s, v7.2s \n"
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"trn1 v19.2s, v3.2s, v7.2s \n"
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"trn2 v22.2s, v2.2s, v6.2s \n"
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"trn1 v18.2s, v2.2s, v6.2s \n"
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2014-09-13 23:40:36 +00:00
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2016-01-11 17:19:48 +00:00
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"mov %0, %2 \n"
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2014-09-13 23:40:36 +00:00
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MEMACCESS(0)
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2016-01-11 17:19:48 +00:00
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"st1 {v17.8b}, [%0], %6 \n"
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2014-09-13 23:40:36 +00:00
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MEMACCESS(0)
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2016-01-11 17:19:48 +00:00
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"st1 {v16.8b}, [%0], %6 \n"
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2014-09-13 23:40:36 +00:00
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MEMACCESS(0)
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2016-01-11 17:19:48 +00:00
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"st1 {v19.8b}, [%0], %6 \n"
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2014-09-13 23:40:36 +00:00
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MEMACCESS(0)
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2016-01-11 17:19:48 +00:00
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"st1 {v18.8b}, [%0], %6 \n"
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2014-09-13 23:40:36 +00:00
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MEMACCESS(0)
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2016-01-11 17:19:48 +00:00
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"st1 {v21.8b}, [%0], %6 \n"
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2014-09-13 23:40:36 +00:00
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MEMACCESS(0)
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2016-01-11 17:19:48 +00:00
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"st1 {v20.8b}, [%0], %6 \n"
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2014-09-13 23:40:36 +00:00
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MEMACCESS(0)
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2016-01-11 17:19:48 +00:00
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"st1 {v23.8b}, [%0], %6 \n"
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2014-09-13 23:40:36 +00:00
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MEMACCESS(0)
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2016-01-11 17:19:48 +00:00
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"st1 {v22.8b}, [%0] \n"
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2014-09-13 23:40:36 +00:00
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2016-01-11 17:19:48 +00:00
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"add %1, %1, #8 \n" // src += 8
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"add %2, %2, %6, lsl #3 \n" // dst += 8 * dst_stride
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"subs %3, %3, #8 \n" // w -= 8
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"b.ge 1b \n"
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2014-09-13 23:40:36 +00:00
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// add 8 back to counter. if the result is 0 there are
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// no residuals.
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2016-01-11 17:19:48 +00:00
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"adds %3, %3, #8 \n"
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"b.eq 4f \n"
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2014-09-13 23:40:36 +00:00
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// some residual, so between 1 and 7 lines left to transpose
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2016-01-11 17:19:48 +00:00
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"cmp %3, #2 \n"
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"b.lt 3f \n"
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2014-09-13 23:40:36 +00:00
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2016-01-11 17:19:48 +00:00
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"cmp %3, #4 \n"
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"b.lt 2f \n"
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2014-09-13 23:40:36 +00:00
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// 4x8 block
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2016-01-11 17:19:48 +00:00
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"mov %0, %1 \n"
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2014-09-13 23:40:36 +00:00
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MEMACCESS(0)
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2016-01-11 17:19:48 +00:00
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"ld1 {v0.s}[0], [%0], %5 \n"
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2014-09-13 23:40:36 +00:00
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MEMACCESS(0)
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2016-01-11 17:19:48 +00:00
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"ld1 {v0.s}[1], [%0], %5 \n"
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2014-09-13 23:40:36 +00:00
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MEMACCESS(0)
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2016-01-11 17:19:48 +00:00
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"ld1 {v0.s}[2], [%0], %5 \n"
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2014-09-13 23:40:36 +00:00
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MEMACCESS(0)
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2016-01-11 17:19:48 +00:00
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"ld1 {v0.s}[3], [%0], %5 \n"
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2014-09-13 23:40:36 +00:00
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MEMACCESS(0)
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2016-01-11 17:19:48 +00:00
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"ld1 {v1.s}[0], [%0], %5 \n"
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2014-09-13 23:40:36 +00:00
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MEMACCESS(0)
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2016-01-11 17:19:48 +00:00
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"ld1 {v1.s}[1], [%0], %5 \n"
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2014-09-13 23:40:36 +00:00
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MEMACCESS(0)
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2016-01-11 17:19:48 +00:00
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"ld1 {v1.s}[2], [%0], %5 \n"
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2014-09-13 23:40:36 +00:00
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MEMACCESS(0)
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2016-01-11 17:19:48 +00:00
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"ld1 {v1.s}[3], [%0] \n"
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2014-09-13 23:40:36 +00:00
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2016-01-11 17:19:48 +00:00
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"mov %0, %2 \n"
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2014-09-13 23:40:36 +00:00
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2016-01-11 17:19:48 +00:00
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MEMACCESS(4)
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"ld1 {v2.16b}, [%4] \n"
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2014-09-13 23:40:36 +00:00
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2016-01-11 17:19:48 +00:00
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"tbl v3.16b, {v0.16b}, v2.16b \n"
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"tbl v0.16b, {v1.16b}, v2.16b \n"
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2014-09-13 23:40:36 +00:00
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// TODO(frkoenig): Rework shuffle above to
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// write out with 4 instead of 8 writes.
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MEMACCESS(0)
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2016-01-11 17:19:48 +00:00
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"st1 {v3.s}[0], [%0], %6 \n"
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2014-09-13 23:40:36 +00:00
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MEMACCESS(0)
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2016-01-11 17:19:48 +00:00
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"st1 {v3.s}[1], [%0], %6 \n"
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2014-09-13 23:40:36 +00:00
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MEMACCESS(0)
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2016-01-11 17:19:48 +00:00
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"st1 {v3.s}[2], [%0], %6 \n"
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2014-09-13 23:40:36 +00:00
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MEMACCESS(0)
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2016-01-11 17:19:48 +00:00
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"st1 {v3.s}[3], [%0] \n"
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2014-09-13 23:40:36 +00:00
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2016-01-11 17:19:48 +00:00
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"add %0, %2, #4 \n"
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2014-09-13 23:40:36 +00:00
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MEMACCESS(0)
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2016-01-11 17:19:48 +00:00
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"st1 {v0.s}[0], [%0], %6 \n"
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2014-09-13 23:40:36 +00:00
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MEMACCESS(0)
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2016-01-11 17:19:48 +00:00
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"st1 {v0.s}[1], [%0], %6 \n"
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2014-09-13 23:40:36 +00:00
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MEMACCESS(0)
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2016-01-11 17:19:48 +00:00
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"st1 {v0.s}[2], [%0], %6 \n"
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2014-09-13 23:40:36 +00:00
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MEMACCESS(0)
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2016-01-11 17:19:48 +00:00
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"st1 {v0.s}[3], [%0] \n"
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2014-09-13 23:40:36 +00:00
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2016-01-11 17:19:48 +00:00
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"add %1, %1, #4 \n" // src += 4
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"add %2, %2, %6, lsl #2 \n" // dst += 4 * dst_stride
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"subs %3, %3, #4 \n" // w -= 4
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"b.eq 4f \n"
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2014-09-13 23:40:36 +00:00
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// some residual, check to see if it includes a 2x8 block,
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// or less
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2016-01-11 17:19:48 +00:00
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"cmp %3, #2 \n"
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"b.lt 3f \n"
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2014-09-13 23:40:36 +00:00
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// 2x8 block
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2016-01-11 17:19:48 +00:00
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"2: \n"
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"mov %0, %1 \n"
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2014-09-13 23:40:36 +00:00
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MEMACCESS(0)
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2016-01-11 17:19:48 +00:00
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"ld1 {v0.h}[0], [%0], %5 \n"
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2014-09-13 23:40:36 +00:00
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MEMACCESS(0)
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2016-01-11 17:19:48 +00:00
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"ld1 {v1.h}[0], [%0], %5 \n"
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2014-09-13 23:40:36 +00:00
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MEMACCESS(0)
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2016-01-11 17:19:48 +00:00
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"ld1 {v0.h}[1], [%0], %5 \n"
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2014-09-13 23:40:36 +00:00
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MEMACCESS(0)
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2016-01-11 17:19:48 +00:00
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"ld1 {v1.h}[1], [%0], %5 \n"
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2014-09-13 23:40:36 +00:00
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MEMACCESS(0)
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2016-01-11 17:19:48 +00:00
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"ld1 {v0.h}[2], [%0], %5 \n"
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2014-09-13 23:40:36 +00:00
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MEMACCESS(0)
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2016-01-11 17:19:48 +00:00
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"ld1 {v1.h}[2], [%0], %5 \n"
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2014-09-13 23:40:36 +00:00
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MEMACCESS(0)
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2016-01-11 17:19:48 +00:00
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"ld1 {v0.h}[3], [%0], %5 \n"
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2014-09-13 23:40:36 +00:00
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MEMACCESS(0)
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2016-01-11 17:19:48 +00:00
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"ld1 {v1.h}[3], [%0] \n"
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2014-09-13 23:40:36 +00:00
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2016-01-11 17:19:48 +00:00
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"trn2 v2.8b, v0.8b, v1.8b \n"
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"trn1 v3.8b, v0.8b, v1.8b \n"
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2014-09-13 23:40:36 +00:00
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2016-01-11 17:19:48 +00:00
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"mov %0, %2 \n"
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2014-09-13 23:40:36 +00:00
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MEMACCESS(0)
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2016-01-11 17:19:48 +00:00
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"st1 {v3.8b}, [%0], %6 \n"
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2014-09-13 23:40:36 +00:00
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MEMACCESS(0)
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2016-01-11 17:19:48 +00:00
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"st1 {v2.8b}, [%0] \n"
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2014-09-13 23:40:36 +00:00
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2016-01-11 17:19:48 +00:00
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"add %1, %1, #2 \n" // src += 2
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"add %2, %2, %6, lsl #1 \n" // dst += 2 * dst_stride
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"subs %3, %3, #2 \n" // w -= 2
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"b.eq 4f \n"
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2014-09-13 23:40:36 +00:00
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// 1x8 block
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2016-01-11 17:19:48 +00:00
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"3: \n"
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2014-09-13 23:40:36 +00:00
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MEMACCESS(1)
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2016-01-11 17:19:48 +00:00
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"ld1 {v0.b}[0], [%1], %5 \n"
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2014-09-13 23:40:36 +00:00
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MEMACCESS(1)
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2016-01-11 17:19:48 +00:00
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"ld1 {v0.b}[1], [%1], %5 \n"
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2014-09-13 23:40:36 +00:00
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MEMACCESS(1)
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2016-01-11 17:19:48 +00:00
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|
|
"ld1 {v0.b}[2], [%1], %5 \n"
|
2014-09-13 23:40:36 +00:00
|
|
|
MEMACCESS(1)
|
2016-01-11 17:19:48 +00:00
|
|
|
"ld1 {v0.b}[3], [%1], %5 \n"
|
2014-09-13 23:40:36 +00:00
|
|
|
MEMACCESS(1)
|
2016-01-11 17:19:48 +00:00
|
|
|
"ld1 {v0.b}[4], [%1], %5 \n"
|
2014-09-13 23:40:36 +00:00
|
|
|
MEMACCESS(1)
|
2016-01-11 17:19:48 +00:00
|
|
|
"ld1 {v0.b}[5], [%1], %5 \n"
|
2014-09-13 23:40:36 +00:00
|
|
|
MEMACCESS(1)
|
2016-01-11 17:19:48 +00:00
|
|
|
"ld1 {v0.b}[6], [%1], %5 \n"
|
2014-09-13 23:40:36 +00:00
|
|
|
MEMACCESS(1)
|
2016-01-11 17:19:48 +00:00
|
|
|
"ld1 {v0.b}[7], [%1] \n"
|
|
|
|
|
|
|
|
|
|
MEMACCESS(2)
|
|
|
|
|
"st1 {v0.8b}, [%2] \n"
|
|
|
|
|
|
|
|
|
|
"4: \n"
|
|
|
|
|
|
2016-05-25 21:49:47 +00:00
|
|
|
: "=&r"(src_temp), // %0
|
2016-01-11 17:19:48 +00:00
|
|
|
"+r"(src), // %1
|
|
|
|
|
"+r"(dst), // %2
|
|
|
|
|
"+r"(width64) // %3
|
|
|
|
|
: "r"(&kVTbl4x4Transpose), // %4
|
|
|
|
|
"r"(static_cast<ptrdiff_t>(src_stride)), // %5
|
|
|
|
|
"r"(static_cast<ptrdiff_t>(dst_stride)) // %6
|
|
|
|
|
: "memory", "cc", "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v16",
|
|
|
|
|
"v17", "v18", "v19", "v20", "v21", "v22", "v23"
|
2014-09-13 23:40:36 +00:00
|
|
|
);
|
|
|
|
|
}
|
|
|
|
|
|
2016-01-11 17:19:48 +00:00
|
|
|
static uint8 kVTbl4x4TransposeDi[32] =
|
|
|
|
|
{ 0, 16, 32, 48, 2, 18, 34, 50, 4, 20, 36, 52, 6, 22, 38, 54,
|
|
|
|
|
1, 17, 33, 49, 3, 19, 35, 51, 5, 21, 37, 53, 7, 23, 39, 55};
|
2014-09-13 23:40:36 +00:00
|
|
|
|
|
|
|
|
void TransposeUVWx8_NEON(const uint8* src, int src_stride,
|
|
|
|
|
uint8* dst_a, int dst_stride_a,
|
|
|
|
|
uint8* dst_b, int dst_stride_b,
|
|
|
|
|
int width) {
|
2016-05-25 21:49:47 +00:00
|
|
|
const uint8* src_temp;
|
2016-01-11 17:19:48 +00:00
|
|
|
int64 width64 = (int64) width; // Work around clang 3.4 warning.
|
2014-09-13 23:40:36 +00:00
|
|
|
asm volatile (
|
|
|
|
|
// loops are on blocks of 8. loop will stop when
|
|
|
|
|
// counter gets to or below 0. starting the counter
|
|
|
|
|
// at w-8 allow for this
|
2016-01-11 17:19:48 +00:00
|
|
|
"sub %4, %4, #8 \n"
|
2014-09-13 23:40:36 +00:00
|
|
|
|
|
|
|
|
// handle 8x8 blocks. this should be the majority of the plane
|
|
|
|
|
"1: \n"
|
2016-01-11 17:19:48 +00:00
|
|
|
"mov %0, %1 \n"
|
2014-09-13 23:40:36 +00:00
|
|
|
|
2016-01-11 17:19:48 +00:00
|
|
|
MEMACCESS(0)
|
|
|
|
|
"ld1 {v0.16b}, [%0], %5 \n"
|
|
|
|
|
MEMACCESS(0)
|
|
|
|
|
"ld1 {v1.16b}, [%0], %5 \n"
|
|
|
|
|
MEMACCESS(0)
|
|
|
|
|
"ld1 {v2.16b}, [%0], %5 \n"
|
|
|
|
|
MEMACCESS(0)
|
|
|
|
|
"ld1 {v3.16b}, [%0], %5 \n"
|
|
|
|
|
MEMACCESS(0)
|
|
|
|
|
"ld1 {v4.16b}, [%0], %5 \n"
|
|
|
|
|
MEMACCESS(0)
|
|
|
|
|
"ld1 {v5.16b}, [%0], %5 \n"
|
|
|
|
|
MEMACCESS(0)
|
|
|
|
|
"ld1 {v6.16b}, [%0], %5 \n"
|
|
|
|
|
MEMACCESS(0)
|
|
|
|
|
"ld1 {v7.16b}, [%0] \n"
|
2014-09-13 23:40:36 +00:00
|
|
|
|
2016-01-11 17:19:48 +00:00
|
|
|
"trn1 v16.16b, v0.16b, v1.16b \n"
|
|
|
|
|
"trn2 v17.16b, v0.16b, v1.16b \n"
|
|
|
|
|
"trn1 v18.16b, v2.16b, v3.16b \n"
|
|
|
|
|
"trn2 v19.16b, v2.16b, v3.16b \n"
|
|
|
|
|
"trn1 v20.16b, v4.16b, v5.16b \n"
|
|
|
|
|
"trn2 v21.16b, v4.16b, v5.16b \n"
|
|
|
|
|
"trn1 v22.16b, v6.16b, v7.16b \n"
|
|
|
|
|
"trn2 v23.16b, v6.16b, v7.16b \n"
|
2014-09-13 23:40:36 +00:00
|
|
|
|
2016-01-11 17:19:48 +00:00
|
|
|
"trn1 v0.8h, v16.8h, v18.8h \n"
|
|
|
|
|
"trn2 v1.8h, v16.8h, v18.8h \n"
|
|
|
|
|
"trn1 v2.8h, v20.8h, v22.8h \n"
|
|
|
|
|
"trn2 v3.8h, v20.8h, v22.8h \n"
|
|
|
|
|
"trn1 v4.8h, v17.8h, v19.8h \n"
|
|
|
|
|
"trn2 v5.8h, v17.8h, v19.8h \n"
|
|
|
|
|
"trn1 v6.8h, v21.8h, v23.8h \n"
|
|
|
|
|
"trn2 v7.8h, v21.8h, v23.8h \n"
|
2014-09-13 23:40:36 +00:00
|
|
|
|
2016-01-11 17:19:48 +00:00
|
|
|
"trn1 v16.4s, v0.4s, v2.4s \n"
|
|
|
|
|
"trn2 v17.4s, v0.4s, v2.4s \n"
|
|
|
|
|
"trn1 v18.4s, v1.4s, v3.4s \n"
|
|
|
|
|
"trn2 v19.4s, v1.4s, v3.4s \n"
|
|
|
|
|
"trn1 v20.4s, v4.4s, v6.4s \n"
|
|
|
|
|
"trn2 v21.4s, v4.4s, v6.4s \n"
|
|
|
|
|
"trn1 v22.4s, v5.4s, v7.4s \n"
|
|
|
|
|
"trn2 v23.4s, v5.4s, v7.4s \n"
|
2014-09-13 23:40:36 +00:00
|
|
|
|
2016-01-11 17:19:48 +00:00
|
|
|
"mov %0, %2 \n"
|
2014-09-13 23:40:36 +00:00
|
|
|
|
|
|
|
|
MEMACCESS(0)
|
2016-01-11 17:19:48 +00:00
|
|
|
"st1 {v16.d}[0], [%0], %6 \n"
|
2014-09-13 23:40:36 +00:00
|
|
|
MEMACCESS(0)
|
2016-01-11 17:19:48 +00:00
|
|
|
"st1 {v18.d}[0], [%0], %6 \n"
|
2014-09-13 23:40:36 +00:00
|
|
|
MEMACCESS(0)
|
2016-01-11 17:19:48 +00:00
|
|
|
"st1 {v17.d}[0], [%0], %6 \n"
|
2014-09-13 23:40:36 +00:00
|
|
|
MEMACCESS(0)
|
2016-01-11 17:19:48 +00:00
|
|
|
"st1 {v19.d}[0], [%0], %6 \n"
|
2014-09-13 23:40:36 +00:00
|
|
|
MEMACCESS(0)
|
2016-01-11 17:19:48 +00:00
|
|
|
"st1 {v16.d}[1], [%0], %6 \n"
|
2014-09-13 23:40:36 +00:00
|
|
|
MEMACCESS(0)
|
2016-01-11 17:19:48 +00:00
|
|
|
"st1 {v18.d}[1], [%0], %6 \n"
|
2014-09-13 23:40:36 +00:00
|
|
|
MEMACCESS(0)
|
2016-01-11 17:19:48 +00:00
|
|
|
"st1 {v17.d}[1], [%0], %6 \n"
|
2014-09-13 23:40:36 +00:00
|
|
|
MEMACCESS(0)
|
2016-01-11 17:19:48 +00:00
|
|
|
"st1 {v19.d}[1], [%0] \n"
|
2014-09-13 23:40:36 +00:00
|
|
|
|
2016-01-11 17:19:48 +00:00
|
|
|
"mov %0, %3 \n"
|
2014-09-13 23:40:36 +00:00
|
|
|
|
|
|
|
|
MEMACCESS(0)
|
2016-01-11 17:19:48 +00:00
|
|
|
"st1 {v20.d}[0], [%0], %7 \n"
|
2014-09-13 23:40:36 +00:00
|
|
|
MEMACCESS(0)
|
2016-01-11 17:19:48 +00:00
|
|
|
"st1 {v22.d}[0], [%0], %7 \n"
|
2014-09-13 23:40:36 +00:00
|
|
|
MEMACCESS(0)
|
2016-01-11 17:19:48 +00:00
|
|
|
"st1 {v21.d}[0], [%0], %7 \n"
|
2014-09-13 23:40:36 +00:00
|
|
|
MEMACCESS(0)
|
2016-01-11 17:19:48 +00:00
|
|
|
"st1 {v23.d}[0], [%0], %7 \n"
|
2014-09-13 23:40:36 +00:00
|
|
|
MEMACCESS(0)
|
2016-01-11 17:19:48 +00:00
|
|
|
"st1 {v20.d}[1], [%0], %7 \n"
|
2014-09-13 23:40:36 +00:00
|
|
|
MEMACCESS(0)
|
2016-01-11 17:19:48 +00:00
|
|
|
"st1 {v22.d}[1], [%0], %7 \n"
|
2014-09-13 23:40:36 +00:00
|
|
|
MEMACCESS(0)
|
2016-01-11 17:19:48 +00:00
|
|
|
"st1 {v21.d}[1], [%0], %7 \n"
|
2014-09-13 23:40:36 +00:00
|
|
|
MEMACCESS(0)
|
2016-01-11 17:19:48 +00:00
|
|
|
"st1 {v23.d}[1], [%0] \n"
|
2014-09-13 23:40:36 +00:00
|
|
|
|
2016-01-11 17:19:48 +00:00
|
|
|
"add %1, %1, #16 \n" // src += 8*2
|
|
|
|
|
"add %2, %2, %6, lsl #3 \n" // dst_a += 8 * dst_stride_a
|
|
|
|
|
"add %3, %3, %7, lsl #3 \n" // dst_b += 8 * dst_stride_b
|
|
|
|
|
"subs %4, %4, #8 \n" // w -= 8
|
|
|
|
|
"b.ge 1b \n"
|
2014-09-13 23:40:36 +00:00
|
|
|
|
|
|
|
|
// add 8 back to counter. if the result is 0 there are
|
|
|
|
|
// no residuals.
|
2016-01-11 17:19:48 +00:00
|
|
|
"adds %4, %4, #8 \n"
|
|
|
|
|
"b.eq 4f \n"
|
2014-09-13 23:40:36 +00:00
|
|
|
|
|
|
|
|
// some residual, so between 1 and 7 lines left to transpose
|
2016-01-11 17:19:48 +00:00
|
|
|
"cmp %4, #2 \n"
|
|
|
|
|
"b.lt 3f \n"
|
2014-09-13 23:40:36 +00:00
|
|
|
|
2016-01-11 17:19:48 +00:00
|
|
|
"cmp %4, #4 \n"
|
|
|
|
|
"b.lt 2f \n"
|
2014-09-13 23:40:36 +00:00
|
|
|
|
|
|
|
|
// TODO(frkoenig): Clean this up
|
|
|
|
|
// 4x8 block
|
2016-01-11 17:19:48 +00:00
|
|
|
"mov %0, %1 \n"
|
2014-09-13 23:40:36 +00:00
|
|
|
MEMACCESS(0)
|
2016-01-11 17:19:48 +00:00
|
|
|
"ld1 {v0.8b}, [%0], %5 \n"
|
2014-09-13 23:40:36 +00:00
|
|
|
MEMACCESS(0)
|
2016-01-11 17:19:48 +00:00
|
|
|
"ld1 {v1.8b}, [%0], %5 \n"
|
2014-09-13 23:40:36 +00:00
|
|
|
MEMACCESS(0)
|
2016-01-11 17:19:48 +00:00
|
|
|
"ld1 {v2.8b}, [%0], %5 \n"
|
2014-09-13 23:40:36 +00:00
|
|
|
MEMACCESS(0)
|
2016-01-11 17:19:48 +00:00
|
|
|
"ld1 {v3.8b}, [%0], %5 \n"
|
2014-09-13 23:40:36 +00:00
|
|
|
MEMACCESS(0)
|
2016-01-11 17:19:48 +00:00
|
|
|
"ld1 {v4.8b}, [%0], %5 \n"
|
2014-09-13 23:40:36 +00:00
|
|
|
MEMACCESS(0)
|
2016-01-11 17:19:48 +00:00
|
|
|
"ld1 {v5.8b}, [%0], %5 \n"
|
2014-09-13 23:40:36 +00:00
|
|
|
MEMACCESS(0)
|
2016-01-11 17:19:48 +00:00
|
|
|
"ld1 {v6.8b}, [%0], %5 \n"
|
2014-09-13 23:40:36 +00:00
|
|
|
MEMACCESS(0)
|
2016-01-11 17:19:48 +00:00
|
|
|
"ld1 {v7.8b}, [%0] \n"
|
2014-09-13 23:40:36 +00:00
|
|
|
|
|
|
|
|
MEMACCESS(8)
|
2016-01-11 17:19:48 +00:00
|
|
|
"ld1 {v30.16b}, [%8], #16 \n"
|
|
|
|
|
"ld1 {v31.16b}, [%8] \n"
|
2014-09-13 23:40:36 +00:00
|
|
|
|
2016-01-11 17:19:48 +00:00
|
|
|
"tbl v16.16b, {v0.16b, v1.16b, v2.16b, v3.16b}, v30.16b \n"
|
|
|
|
|
"tbl v17.16b, {v0.16b, v1.16b, v2.16b, v3.16b}, v31.16b \n"
|
|
|
|
|
"tbl v18.16b, {v4.16b, v5.16b, v6.16b, v7.16b}, v30.16b \n"
|
|
|
|
|
"tbl v19.16b, {v4.16b, v5.16b, v6.16b, v7.16b}, v31.16b \n"
|
2014-09-13 23:40:36 +00:00
|
|
|
|
2016-01-11 17:19:48 +00:00
|
|
|
"mov %0, %2 \n"
|
2014-09-13 23:40:36 +00:00
|
|
|
|
|
|
|
|
MEMACCESS(0)
|
2016-01-11 17:19:48 +00:00
|
|
|
"st1 {v16.s}[0], [%0], %6 \n"
|
2014-09-13 23:40:36 +00:00
|
|
|
MEMACCESS(0)
|
2016-01-11 17:19:48 +00:00
|
|
|
"st1 {v16.s}[1], [%0], %6 \n"
|
2014-09-13 23:40:36 +00:00
|
|
|
MEMACCESS(0)
|
2016-01-11 17:19:48 +00:00
|
|
|
"st1 {v16.s}[2], [%0], %6 \n"
|
2014-09-13 23:40:36 +00:00
|
|
|
MEMACCESS(0)
|
2016-01-11 17:19:48 +00:00
|
|
|
"st1 {v16.s}[3], [%0], %6 \n"
|
2014-09-13 23:40:36 +00:00
|
|
|
|
2016-01-11 17:19:48 +00:00
|
|
|
"add %0, %2, #4 \n"
|
2014-09-13 23:40:36 +00:00
|
|
|
MEMACCESS(0)
|
2016-01-11 17:19:48 +00:00
|
|
|
"st1 {v18.s}[0], [%0], %6 \n"
|
2014-09-13 23:40:36 +00:00
|
|
|
MEMACCESS(0)
|
2016-01-11 17:19:48 +00:00
|
|
|
"st1 {v18.s}[1], [%0], %6 \n"
|
2014-09-13 23:40:36 +00:00
|
|
|
MEMACCESS(0)
|
2016-01-11 17:19:48 +00:00
|
|
|
"st1 {v18.s}[2], [%0], %6 \n"
|
2014-09-13 23:40:36 +00:00
|
|
|
MEMACCESS(0)
|
2016-01-11 17:19:48 +00:00
|
|
|
"st1 {v18.s}[3], [%0] \n"
|
2014-09-13 23:40:36 +00:00
|
|
|
|
2016-01-11 17:19:48 +00:00
|
|
|
"mov %0, %3 \n"
|
2014-09-13 23:40:36 +00:00
|
|
|
|
|
|
|
|
MEMACCESS(0)
|
2016-01-11 17:19:48 +00:00
|
|
|
"st1 {v17.s}[0], [%0], %7 \n"
|
2014-09-13 23:40:36 +00:00
|
|
|
MEMACCESS(0)
|
2016-01-11 17:19:48 +00:00
|
|
|
"st1 {v17.s}[1], [%0], %7 \n"
|
2014-09-13 23:40:36 +00:00
|
|
|
MEMACCESS(0)
|
2016-01-11 17:19:48 +00:00
|
|
|
"st1 {v17.s}[2], [%0], %7 \n"
|
2014-09-13 23:40:36 +00:00
|
|
|
MEMACCESS(0)
|
2016-01-11 17:19:48 +00:00
|
|
|
"st1 {v17.s}[3], [%0], %7 \n"
|
2014-09-13 23:40:36 +00:00
|
|
|
|
2016-01-11 17:19:48 +00:00
|
|
|
"add %0, %3, #4 \n"
|
2014-09-13 23:40:36 +00:00
|
|
|
MEMACCESS(0)
|
2016-01-11 17:19:48 +00:00
|
|
|
"st1 {v19.s}[0], [%0], %7 \n"
|
2014-09-13 23:40:36 +00:00
|
|
|
MEMACCESS(0)
|
2016-01-11 17:19:48 +00:00
|
|
|
"st1 {v19.s}[1], [%0], %7 \n"
|
2014-09-13 23:40:36 +00:00
|
|
|
MEMACCESS(0)
|
2016-01-11 17:19:48 +00:00
|
|
|
"st1 {v19.s}[2], [%0], %7 \n"
|
2014-09-13 23:40:36 +00:00
|
|
|
MEMACCESS(0)
|
2016-01-11 17:19:48 +00:00
|
|
|
"st1 {v19.s}[3], [%0] \n"
|
2014-09-13 23:40:36 +00:00
|
|
|
|
2016-01-11 17:19:48 +00:00
|
|
|
"add %1, %1, #8 \n" // src += 4 * 2
|
|
|
|
|
"add %2, %2, %6, lsl #2 \n" // dst_a += 4 * dst_stride_a
|
|
|
|
|
"add %3, %3, %7, lsl #2 \n" // dst_b += 4 * dst_stride_b
|
|
|
|
|
"subs %4, %4, #4 \n" // w -= 4
|
|
|
|
|
"b.eq 4f \n"
|
2014-09-13 23:40:36 +00:00
|
|
|
|
|
|
|
|
// some residual, check to see if it includes a 2x8 block,
|
|
|
|
|
// or less
|
2016-01-11 17:19:48 +00:00
|
|
|
"cmp %4, #2 \n"
|
|
|
|
|
"b.lt 3f \n"
|
2014-09-13 23:40:36 +00:00
|
|
|
|
|
|
|
|
// 2x8 block
|
|
|
|
|
"2: \n"
|
2016-01-11 17:19:48 +00:00
|
|
|
"mov %0, %1 \n"
|
2014-09-13 23:40:36 +00:00
|
|
|
MEMACCESS(0)
|
2016-01-11 17:19:48 +00:00
|
|
|
"ld2 {v0.h, v1.h}[0], [%0], %5 \n"
|
2014-09-13 23:40:36 +00:00
|
|
|
MEMACCESS(0)
|
2016-01-11 17:19:48 +00:00
|
|
|
"ld2 {v2.h, v3.h}[0], [%0], %5 \n"
|
2014-09-13 23:40:36 +00:00
|
|
|
MEMACCESS(0)
|
2016-01-11 17:19:48 +00:00
|
|
|
"ld2 {v0.h, v1.h}[1], [%0], %5 \n"
|
2014-09-13 23:40:36 +00:00
|
|
|
MEMACCESS(0)
|
2016-01-11 17:19:48 +00:00
|
|
|
"ld2 {v2.h, v3.h}[1], [%0], %5 \n"
|
2014-09-13 23:40:36 +00:00
|
|
|
MEMACCESS(0)
|
2016-01-11 17:19:48 +00:00
|
|
|
"ld2 {v0.h, v1.h}[2], [%0], %5 \n"
|
2014-09-13 23:40:36 +00:00
|
|
|
MEMACCESS(0)
|
2016-01-11 17:19:48 +00:00
|
|
|
"ld2 {v2.h, v3.h}[2], [%0], %5 \n"
|
2014-09-13 23:40:36 +00:00
|
|
|
MEMACCESS(0)
|
2016-01-11 17:19:48 +00:00
|
|
|
"ld2 {v0.h, v1.h}[3], [%0], %5 \n"
|
2014-09-13 23:40:36 +00:00
|
|
|
MEMACCESS(0)
|
2016-01-11 17:19:48 +00:00
|
|
|
"ld2 {v2.h, v3.h}[3], [%0] \n"
|
2014-09-13 23:40:36 +00:00
|
|
|
|
2016-01-11 17:19:48 +00:00
|
|
|
"trn1 v4.8b, v0.8b, v2.8b \n"
|
|
|
|
|
"trn2 v5.8b, v0.8b, v2.8b \n"
|
|
|
|
|
"trn1 v6.8b, v1.8b, v3.8b \n"
|
|
|
|
|
"trn2 v7.8b, v1.8b, v3.8b \n"
|
2014-09-13 23:40:36 +00:00
|
|
|
|
2016-01-11 17:19:48 +00:00
|
|
|
"mov %0, %2 \n"
|
2014-09-13 23:40:36 +00:00
|
|
|
|
|
|
|
|
MEMACCESS(0)
|
2016-01-11 17:19:48 +00:00
|
|
|
"st1 {v4.d}[0], [%0], %6 \n"
|
2014-09-13 23:40:36 +00:00
|
|
|
MEMACCESS(0)
|
2016-01-11 17:19:48 +00:00
|
|
|
"st1 {v6.d}[0], [%0] \n"
|
2014-09-13 23:40:36 +00:00
|
|
|
|
2016-01-11 17:19:48 +00:00
|
|
|
"mov %0, %3 \n"
|
2014-09-13 23:40:36 +00:00
|
|
|
|
|
|
|
|
MEMACCESS(0)
|
2016-01-11 17:19:48 +00:00
|
|
|
"st1 {v5.d}[0], [%0], %7 \n"
|
2014-09-13 23:40:36 +00:00
|
|
|
MEMACCESS(0)
|
2016-01-11 17:19:48 +00:00
|
|
|
"st1 {v7.d}[0], [%0] \n"
|
2014-09-13 23:40:36 +00:00
|
|
|
|
2016-01-11 17:19:48 +00:00
|
|
|
"add %1, %1, #4 \n" // src += 2 * 2
|
|
|
|
|
"add %2, %2, %6, lsl #1 \n" // dst_a += 2 * dst_stride_a
|
|
|
|
|
"add %3, %3, %7, lsl #1 \n" // dst_b += 2 * dst_stride_b
|
|
|
|
|
"subs %4, %4, #2 \n" // w -= 2
|
|
|
|
|
"b.eq 4f \n"
|
2014-09-13 23:40:36 +00:00
|
|
|
|
|
|
|
|
// 1x8 block
|
|
|
|
|
"3: \n"
|
|
|
|
|
MEMACCESS(1)
|
2016-01-11 17:19:48 +00:00
|
|
|
"ld2 {v0.b, v1.b}[0], [%1], %5 \n"
|
2014-09-13 23:40:36 +00:00
|
|
|
MEMACCESS(1)
|
2016-01-11 17:19:48 +00:00
|
|
|
"ld2 {v0.b, v1.b}[1], [%1], %5 \n"
|
2014-09-13 23:40:36 +00:00
|
|
|
MEMACCESS(1)
|
2016-01-11 17:19:48 +00:00
|
|
|
"ld2 {v0.b, v1.b}[2], [%1], %5 \n"
|
2014-09-13 23:40:36 +00:00
|
|
|
MEMACCESS(1)
|
2016-01-11 17:19:48 +00:00
|
|
|
"ld2 {v0.b, v1.b}[3], [%1], %5 \n"
|
2014-09-13 23:40:36 +00:00
|
|
|
MEMACCESS(1)
|
2016-01-11 17:19:48 +00:00
|
|
|
"ld2 {v0.b, v1.b}[4], [%1], %5 \n"
|
2014-09-13 23:40:36 +00:00
|
|
|
MEMACCESS(1)
|
2016-01-11 17:19:48 +00:00
|
|
|
"ld2 {v0.b, v1.b}[5], [%1], %5 \n"
|
2014-09-13 23:40:36 +00:00
|
|
|
MEMACCESS(1)
|
2016-01-11 17:19:48 +00:00
|
|
|
"ld2 {v0.b, v1.b}[6], [%1], %5 \n"
|
2014-09-13 23:40:36 +00:00
|
|
|
MEMACCESS(1)
|
2016-01-11 17:19:48 +00:00
|
|
|
"ld2 {v0.b, v1.b}[7], [%1] \n"
|
2014-09-13 23:40:36 +00:00
|
|
|
|
2016-01-11 17:19:48 +00:00
|
|
|
MEMACCESS(2)
|
|
|
|
|
"st1 {v0.d}[0], [%2] \n"
|
2014-09-13 23:40:36 +00:00
|
|
|
MEMACCESS(3)
|
2016-01-11 17:19:48 +00:00
|
|
|
"st1 {v1.d}[0], [%3] \n"
|
2014-09-13 23:40:36 +00:00
|
|
|
|
|
|
|
|
"4: \n"
|
|
|
|
|
|
2016-05-25 21:49:47 +00:00
|
|
|
: "=&r"(src_temp), // %0
|
2016-01-11 17:19:48 +00:00
|
|
|
"+r"(src), // %1
|
|
|
|
|
"+r"(dst_a), // %2
|
|
|
|
|
"+r"(dst_b), // %3
|
|
|
|
|
"+r"(width64) // %4
|
|
|
|
|
: "r"(static_cast<ptrdiff_t>(src_stride)), // %5
|
|
|
|
|
"r"(static_cast<ptrdiff_t>(dst_stride_a)), // %6
|
|
|
|
|
"r"(static_cast<ptrdiff_t>(dst_stride_b)), // %7
|
|
|
|
|
"r"(&kVTbl4x4TransposeDi) // %8
|
2014-09-13 23:40:36 +00:00
|
|
|
: "memory", "cc",
|
2016-01-11 17:19:48 +00:00
|
|
|
"v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7",
|
|
|
|
|
"v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23",
|
|
|
|
|
"v30", "v31"
|
2014-09-13 23:40:36 +00:00
|
|
|
);
|
|
|
|
|
}
|
2016-01-11 17:19:48 +00:00
|
|
|
#endif // !defined(LIBYUV_DISABLE_NEON) && defined(__aarch64__)
|
2014-09-13 23:40:36 +00:00
|
|
|
|
|
|
|
|
#ifdef __cplusplus
|
|
|
|
|
} // extern "C"
|
|
|
|
|
} // namespace libyuv
|
|
|
|
|
#endif
|
