289 lines
9.9 KiB
C
289 lines
9.9 KiB
C
/* Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
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* All rights reserved.
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*
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* This package is an SSL implementation written
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* by Eric Young (eay@cryptsoft.com).
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* The implementation was written so as to conform with Netscapes SSL.
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*
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* This library is free for commercial and non-commercial use as long as
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* the following conditions are aheared to. The following conditions
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* apply to all code found in this distribution, be it the RC4, RSA,
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* lhash, DES, etc., code; not just the SSL code. The SSL documentation
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* included with this distribution is covered by the same copyright terms
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* except that the holder is Tim Hudson (tjh@cryptsoft.com).
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*
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* Copyright remains Eric Young's, and as such any Copyright notices in
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* the code are not to be removed.
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* If this package is used in a product, Eric Young should be given attribution
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* as the author of the parts of the library used.
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* This can be in the form of a textual message at program startup or
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* in documentation (online or textual) provided with the package.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* "This product includes cryptographic software written by
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* Eric Young (eay@cryptsoft.com)"
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* The word 'cryptographic' can be left out if the rouines from the library
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* being used are not cryptographic related :-).
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* 4. If you include any Windows specific code (or a derivative thereof) from
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* the apps directory (application code) you must include an acknowledgement:
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* "This product includes software written by Tim Hudson (tjh@cryptsoft.com)"
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*
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* THIS SOFTWARE IS PROVIDED BY ERIC YOUNG ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* The licence and distribution terms for any publically available version or
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* derivative of this code cannot be changed. i.e. this code cannot simply be
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* copied and put under another distribution licence
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* [including the GNU Public Licence.] */
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#if !defined(__STDC_FORMAT_MACROS)
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#define __STDC_FORMAT_MACROS
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#endif
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#include <openssl/cpu.h>
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#if !defined(OPENSSL_NO_ASM) && (defined(OPENSSL_X86) || defined(OPENSSL_X86_64))
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#include <inttypes.h>
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#include <stdio.h>
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#include <stdlib.h>
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#include <string.h>
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#if defined(_MSC_VER)
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OPENSSL_MSVC_PRAGMA(warning(push, 3))
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#include <immintrin.h>
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#include <intrin.h>
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OPENSSL_MSVC_PRAGMA(warning(pop))
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#endif
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#include "internal.h"
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// OPENSSL_cpuid runs the cpuid instruction. |leaf| is passed in as EAX and ECX
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// is set to zero. It writes EAX, EBX, ECX, and EDX to |*out_eax| through
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// |*out_edx|.
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static void OPENSSL_cpuid(uint32_t *out_eax, uint32_t *out_ebx,
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uint32_t *out_ecx, uint32_t *out_edx, uint32_t leaf) {
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#if defined(_MSC_VER)
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int tmp[4];
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__cpuid(tmp, (int)leaf);
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*out_eax = (uint32_t)tmp[0];
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*out_ebx = (uint32_t)tmp[1];
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*out_ecx = (uint32_t)tmp[2];
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*out_edx = (uint32_t)tmp[3];
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#elif defined(__pic__) && defined(OPENSSL_32_BIT)
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// Inline assembly may not clobber the PIC register. For 32-bit, this is EBX.
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// See https://gcc.gnu.org/bugzilla/show_bug.cgi?id=47602.
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__asm__ volatile (
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"xor %%ecx, %%ecx\n"
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"mov %%ebx, %%edi\n"
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"cpuid\n"
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"xchg %%edi, %%ebx\n"
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: "=a"(*out_eax), "=D"(*out_ebx), "=c"(*out_ecx), "=d"(*out_edx)
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: "a"(leaf)
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);
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#else
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__asm__ volatile (
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"xor %%ecx, %%ecx\n"
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"cpuid\n"
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: "=a"(*out_eax), "=b"(*out_ebx), "=c"(*out_ecx), "=d"(*out_edx)
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: "a"(leaf)
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);
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#endif
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}
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// OPENSSL_xgetbv returns the value of an Intel Extended Control Register (XCR).
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// Currently only XCR0 is defined by Intel so |xcr| should always be zero.
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static uint64_t OPENSSL_xgetbv(uint32_t xcr) {
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#if defined(_MSC_VER)
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return (uint64_t)_xgetbv(xcr);
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#else
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uint32_t eax, edx;
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__asm__ volatile ("xgetbv" : "=a"(eax), "=d"(edx) : "c"(xcr));
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return (((uint64_t)edx) << 32) | eax;
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#endif
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}
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// handle_cpu_env applies the value from |in| to the CPUID values in |out[0]|
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// and |out[1]|. See the comment in |OPENSSL_cpuid_setup| about this.
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static void handle_cpu_env(uint32_t *out, const char *in) {
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const int invert = in[0] == '~';
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uint64_t v;
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if (!sscanf(in + invert, "%" PRIu64, &v)) {
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return;
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}
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if (invert) {
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out[0] &= ~v;
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out[1] &= ~(v >> 32);
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} else {
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out[0] = v;
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out[1] = v >> 32;
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}
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}
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void OPENSSL_cpuid_setup(void) {
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// Determine the vendor and maximum input value.
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uint32_t eax, ebx, ecx, edx;
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OPENSSL_cpuid(&eax, &ebx, &ecx, &edx, 0);
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uint32_t num_ids = eax;
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int is_intel = ebx == 0x756e6547 /* Genu */ &&
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edx == 0x49656e69 /* ineI */ &&
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ecx == 0x6c65746e /* ntel */;
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int is_amd = ebx == 0x68747541 /* Auth */ &&
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edx == 0x69746e65 /* enti */ &&
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ecx == 0x444d4163 /* cAMD */;
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int has_amd_xop = 0;
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if (is_amd) {
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// AMD-specific logic.
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// See http://developer.amd.com/wordpress/media/2012/10/254811.pdf
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OPENSSL_cpuid(&eax, &ebx, &ecx, &edx, 0x80000000);
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uint32_t num_extended_ids = eax;
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if (num_extended_ids >= 0x80000001) {
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OPENSSL_cpuid(&eax, &ebx, &ecx, &edx, 0x80000001);
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if (ecx & (1u << 11)) {
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has_amd_xop = 1;
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}
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}
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}
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uint32_t extended_features = 0;
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if (num_ids >= 7) {
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OPENSSL_cpuid(&eax, &ebx, &ecx, &edx, 7);
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extended_features = ebx;
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}
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// Determine the number of cores sharing an L1 data cache to adjust the
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// hyper-threading bit.
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uint32_t cores_per_cache = 0;
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if (is_amd) {
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// AMD CPUs never share an L1 data cache between threads but do set the HTT
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// bit on multi-core CPUs.
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cores_per_cache = 1;
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} else if (num_ids >= 4) {
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// TODO(davidben): The Intel manual says this CPUID leaf enumerates all
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// caches using ECX and doesn't say which is first. Does this matter?
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OPENSSL_cpuid(&eax, &ebx, &ecx, &edx, 4);
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cores_per_cache = 1 + ((eax >> 14) & 0xfff);
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}
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OPENSSL_cpuid(&eax, &ebx, &ecx, &edx, 1);
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// Adjust the hyper-threading bit.
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if (edx & (1u << 28)) {
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uint32_t num_logical_cores = (ebx >> 16) & 0xff;
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if (cores_per_cache == 1 || num_logical_cores <= 1) {
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edx &= ~(1u << 28);
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}
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}
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// Reserved bit #20 was historically repurposed to control the in-memory
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// representation of RC4 state. Always set it to zero.
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edx &= ~(1u << 20);
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// Reserved bit #30 is repurposed to signal an Intel CPU.
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if (is_intel) {
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edx |= (1u << 30);
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// Clear the XSAVE bit on Knights Landing to mimic Silvermont. This enables
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// some Silvermont-specific codepaths which perform better. See OpenSSL
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// commit 64d92d74985ebb3d0be58a9718f9e080a14a8e7f.
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if ((eax & 0x0fff0ff0) == 0x00050670 /* Knights Landing */ ||
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(eax & 0x0fff0ff0) == 0x00080650 /* Knights Mill (per SDE) */) {
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ecx &= ~(1u << 26);
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}
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} else {
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edx &= ~(1u << 30);
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}
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// The SDBG bit is repurposed to denote AMD XOP support.
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if (has_amd_xop) {
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ecx |= (1u << 11);
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} else {
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ecx &= ~(1u << 11);
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}
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uint64_t xcr0 = 0;
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if (ecx & (1u << 27)) {
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// XCR0 may only be queried if the OSXSAVE bit is set.
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xcr0 = OPENSSL_xgetbv(0);
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}
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// See Intel manual, volume 1, section 14.3.
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if ((xcr0 & 6) != 6) {
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// YMM registers cannot be used.
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ecx &= ~(1u << 28); // AVX
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ecx &= ~(1u << 12); // FMA
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ecx &= ~(1u << 11); // AMD XOP
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// Clear AVX2 and AVX512* bits.
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//
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// TODO(davidben): Should bits 17 and 26-28 also be cleared? Upstream
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// doesn't clear those.
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extended_features &=
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~((1u << 5) | (1u << 16) | (1u << 21) | (1u << 30) | (1u << 31));
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}
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// See Intel manual, volume 1, section 15.2.
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if ((xcr0 & 0xe6) != 0xe6) {
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// Clear AVX512F. Note we don't touch other AVX512 extensions because they
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// can be used with YMM.
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extended_features &= ~(1u << 16);
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}
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// Disable ADX instructions on Knights Landing. See OpenSSL commit
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// 64d92d74985ebb3d0be58a9718f9e080a14a8e7f.
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if ((ecx & (1u << 26)) == 0) {
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extended_features &= ~(1u << 19);
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}
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OPENSSL_ia32cap_P[0] = edx;
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OPENSSL_ia32cap_P[1] = ecx;
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OPENSSL_ia32cap_P[2] = extended_features;
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OPENSSL_ia32cap_P[3] = 0;
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const char *env1, *env2;
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env1 = getenv("OPENSSL_ia32cap");
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if (env1 == NULL) {
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return;
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}
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// OPENSSL_ia32cap can contain zero, one or two values, separated with a ':'.
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// Each value is a 64-bit, unsigned value which may start with "0x" to
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// indicate a hex value. Prior to the 64-bit value, a '~' may be given.
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//
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// If '~' isn't present, then the value is taken as the result of the CPUID.
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// Otherwise the value is inverted and ANDed with the probed CPUID result.
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//
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// The first value determines OPENSSL_ia32cap_P[0] and [1]. The second [2]
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// and [3].
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handle_cpu_env(&OPENSSL_ia32cap_P[0], env1);
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env2 = strchr(env1, ':');
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if (env2 != NULL) {
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handle_cpu_env(&OPENSSL_ia32cap_P[2], env2 + 1);
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}
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}
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#endif // !OPENSSL_NO_ASM && (OPENSSL_X86 || OPENSSL_X86_64)
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